1. Field of the Invention
The present invention relates to an internal power supply circuit for use in a semiconductor device, which generates a voltage higher than can be supplied from an external device, to read data from a flash memory, which is capable of flash-erasing stored data, a DRAM (Dynamic Read Only Memory), a SRAM (Static Random Access Memory) or the like.
2. Description of the Related Art
A non-volatile semiconductor memory, such as a flash memory, comprises an EEPROM (Electrically Erasable Programmable Read Only Memory) capable of electrically writing or erasing data. A non-volatile semiconductor memory uses a transistor of a stacked gate type as a memory cell. The transistor has a floating gate FG and a control gate CG, as shown in FIG. 14. Data is written into or read from the memory cell, in such a manner that a threshold voltage is changed by injecting electrons into the floating gate FG or releasing electrons. In a conventional flash memory, a source voltage Vcc is applied to the control gate CG of a selected memory cell when reading data, and the logic concerning "1" or "0" is determined depending on whether or not a current flows in this condition. The threshold voltage of a memory cell, is approximately 2 V when the memory cell is on and is approximately 5 V or more when the memory cell is off.
Conventionally, a power source voltage is set at 5 V, and a gate voltage V.sub.G is set at 5 V when data is read. Further, a conventional flash memory has an arrangement in which a power source voltage of 5 V is directly applied as a voltage for reading data to the control gate CG, and this arrangement does not cause problems. However, as the size of a memory cell becomes smaller and the capacitance thereof is enlarged, the power source voltage of a memory cell must be lowered. Nowadays, a power source voltage of 3 V is substantially standardized in general cases.
If a conventional power source voltage of 5 V is used, the difference between a voltage V.sub.G applied to the control gate CG to read data and a threshold voltage V.sub.TH when the memory cell is on is 3 V: V.sub.G -V.sub.TH =5-2=3 V. On the other hand, if a power source voltage of 3 V is used, the difference is 1 V: V.sub.G -V.sub.TH =3-2=1 V. The latter difference is as small as one third of the former, and a current flowing through a memory cell is therefore reduced. Due to a decrease in the cell-current, the reading speed is lowered and a margin for the power source voltage is reduced.
In order to solve the problems stated above, a method is used in which an external voltage Vccext of 3 V supplied from outside of a chip is boosted in the chip, for example, to generate an internal voltage Vccint of 5 V, and this internal voltage Vccint is applied to the control gate of the memory cell.
FIG. 15 shows a conventional boosting circuit. A boosting circuit is a kind of positive charge pump circuit comprising an oscillator OSC, an inverter circuit IV, a plurality of diodes D, and a plurality of capacitors Cp. In the boosting circuit, an output voltage of the oscillator OSC and a voltage inverted by the inverter circuit IV are alternately supplied to a plurality of capacitors Cp and diodes D, and a predetermined boost voltage is thus generated. The boost voltage outputted from this boosting circuit is applied to a control gate of a memory cell.
FIG. 16 is a schematic view showing a semiconductor memory device, i.e., an example of an arrangement which covers from an address signal input to a word line selection for the memory cell array. A power source voltage Vccext is supplied to an address buffer (referred to as ADB, hereinafter) 21 receiving an address signal ADD. An output signal of the ADB is, for example, supplied to a row address decoder (referred to as RDC, hereinafter) 22 including a pre-decoder. An external voltage Vccext as a power source and an internal voltage Vccint generated by a boosting circuit shown in FIG. 15 are supplied to the RDC 22, and the output signal of the ADB 21 stated above is decoded in the RDC 22. A signal thus decoded of a signal level for the external voltage Vccext system is converted into a signal of a level for an internal voltage Vccint system, and is then supplied to a word line of a memory cell array (referred to as MCA, hereinafter) 23 not shown in figures. This MCA 23 comprises, for example, a plurality of EEPROMs disposed like a matrix. A line address decoder is omitted herefrom.
Meanwhile, a semiconductor device generally has a so-called skew, i.e., a period in which an address signal ADD is not kept constant while the address signal ADD is being changed. While a skew appears, a selection state of the address decoder is not kept stable, and therefore, a large current flows through the address recorder. Consequently, a peak current cannot be maintained at a constant value while an address signal is being changed. A peak current flowing while an address signal is being changed is not so large and therefore does not cause problems. This is because, a DRAM changes address signals in synchronization with clock signals supplied from outside, so that only a small skew occurs and a current flowing in the device can be controlled within a predetermined range of values. However, in case of a static memory, such as a flash memory or a SRAM, which changes address signals without synchronization with clock signals supplied from outside, a skew occurs while an address is being changed, and the skew causes rapid changes in the selection state of the address decoder, so that a large current flows through the address decoder. This is a factor which significantly reduces an internal voltage Vccint.
In the boosting circuit stated above, a current supply ability is limited due to sizes of pattern areas and consumption currents. Once a large current flows as a skew occurs, a long time is required to recover an internal voltage Vccint. More specifically, a peak current generated during a skew is as large as 100 mA, while the current supply ability of a boosting circuit is only about 10 mA. As a result of this, correct data reading cannot be carried out when a reading operation is carried out before the internal voltage Vccint recovers.